High-k metal gate electrode structures formed by separate removal of placeholder materials in transistors of different conductivity type

ABSTRACT

In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present disclosure relates to the fabrication of sophisticated integrated circuits including transistor elements comprising highly capacitive gate structures on the basis of a high-k gate dielectric material of increased permittivity and a work function metal.

2. Description of the Related Art

The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.

Presently, the vast majority of integrated circuits are based on silicon due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.

For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material of a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, usage of high speed transistor elements having an extremely short channel may be substantially restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical signal paths, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with thermal design power requirements for performance driven circuits.

Therefore, replacing silicon dioxide based dielectrics as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide based gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer.

Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance based on the same thickness as a silicon dioxide based layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, in combination with other metals, may be formed so as to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Since the threshold voltage of the transistors, which represents the voltage at which a conductive channel forms in the channel region, is significantly determined by the work function of the metal-containing gate material, an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.

Providing different metal species for adjusting the work function of the gate electrode structures for P-channel transistors and N-channel transistors at an early manufacturing stage may, however, be associated with a plurality of difficulties, which may stem from the fact that a complex patterning sequence may be required during the formation of the sophisticated high-k metal gate stack, which may result in a significant variability of the resulting work function and thus threshold voltage of the completed transistor structures. For instance, during a corresponding manufacturing sequence, the high-k material may be exposed to oxygen, which may result in an increase of layer thickness and thus a reduction of the capacitive coupling. Moreover, a shift of the work function may be observed when forming appropriate work function metals in an early manufacturing stage, which is believed to be caused by a moderately high oxygen affinity of the metal species, in particular during high temperature processes which may typically be required for completing the transistor structures, for instance for forming drain and source regions and the like.

For this reason, in some approaches the initial gate electrode stack may be provided with a high degree of compatibility with conventional polysilicon-based process strategies and the actual electrode metal and the final adjustment of the work function of the transistors may be accomplished in a very advanced manufacturing stage, i.e., after completing the basic transistor structure. In a corresponding replacement gate approach the high-k dielectric material may be formed and may be covered by an appropriate metal-containing material, such as titanium nitride and the like, followed by a standard polysilicon or amorphous silicon material, which may then be patterned on the basis of well-established advanced lithography and etch techniques. Consequently, during the process sequence for patterning the gate electrode structure, the sensitive high-k dielectric material may be protected by the metal-containing material, possibly in combination with sophisticated sidewall spacer structures, thereby substantially avoiding any undue material modification during the further processing. After patterning the gate electrode structure, conventional and well-established process techniques for forming the drain and source regions having the desired complex dopant profile are typically performed. After any high temperature processes, the further processing may be continued, for instance, by forming a metal silicide, if required, followed by the deposition of an interlayer dielectric material, such as silicon nitride in combination with silicon dioxide and the like. In this manufacturing stage, a top surface of the gate electrode structures embedded in the interlayer dielectric material may be exposed, for instance by etch techniques, chemical mechanical polishing (CMP) and the like. In many cases, the polysilicon material may be removed in both types of gate electrode structures in a common etch process and thereafter an appropriate masking regime may be applied in order to selectively fill in an appropriate metal, which may be accomplished by filling in the first metal species and selectively removing the metal species from one of the gate electrode structures. Thereafter, a further metal material may be deposited, thereby obtaining the desired work function for each type of transistor.

Although, in general, this approach may provide advantages in view of reducing process-related non-uniformities in the threshold voltages of the transistors since the high-k dielectric material may be reliably encapsulated during the entire process sequence without requiring an adjustment of the work function and thus the threshold voltage at an early manufacturing stage, the complex process sequence for removing the placeholder material and providing appropriate work function materials for the different types of transistors may also result in a significant degree of variability of the transistor characteristics, which may thus result in offsetting at least some of the advantages obtained by the common processing of the gate electrode structures until the basic transistor configuration is completed. With reference to FIGS. 1 a-1 b, a typical conventional process strategy will be described in order to illustrate in more detail any problems related to the provision of work function materials for P-channel transistors and N-channel transistors on the basis of a replacement gate approach.

FIG. 1 a schematically illustrates a cross-sectional view of a sophisticated semiconductor device 100 in an advanced manufacturing stage, i.e., in a manufacturing stage in which a first transistor 150A, such as a P-channel transistor, and a second transistor 150B, such as an N-channel transistor, are formed in and above active regions 103A, 103B. The active regions 103A, 103B are laterally delineated by isolation structures (not shown) within a semiconductor layer 103, such as a silicon-based semiconductor material. The semiconductor layer 103 is formed above a substrate 101, such as a silicon bulk substrate, a silicon-on-insulator (SOI) substrate and the like. In the case of an SOI substrate, a buried insulating material (not shown) may typically be provided between a crystalline substrate material and the semiconductor layer 103. In the manufacturing stage shown, the transistors 150A, 150B comprise gate electrode structures 160A, 160B, respectively. The gate electrode structures 160A, 160B, which may also be referred to as replacement gate electrode structures, comprise a gate dielectric material 163, which typically comprises a high-k dielectric material, as previously discussed. Moreover, if required, an additional conventional dielectric material, such as a silicon oxide based material, may be provided in the dielectric material 163, for instance in order to provide superior interface conditions with respect to a channel region 152 of the transistors 150A, 150B. Furthermore, a conductive cap material, such as a titanium nitride material 164, is typically formed on the dielectric material 163 in order to confine the sensitive high-k dielectric material. Furthermore, a placeholder material 161, such as a polycrystalline silicon material, may be provided above the conductive cap layer 164 and has been removed during the previous processing so as to provide gate openings 162, which in turn comprise a material layer 166A, as required for adjusting the characteristics of one of the gate electrode structures 160A, 160B. In the example shown in FIG. 1 a, it is assumed that the material layer 166A comprises a metal species that is appropriate for adjusting the work function of the gate electrode structure 160A. As previously discussed, since the material 166A has to be removed from the opening 162 of the gate electrode structure 160B in a later manufacturing stage, a barrier material or etch stop material 167 is frequently provided within the material layer 166A in order to enable the removal of the work function adjusting species from the opening 162 of the gate electrode structure 160B without unduly affecting the sensitive materials 164 and 163 in the gate electrode structure 160B. For example, tantalum nitride is frequently used for this purpose. The gate electrode structures 160A, 160B may further comprise a spacer structure 165 which has any appropriate configuration in terms of individual spacer elements, etch stop materials and the like as is required for the processes for forming the transistors 150A, 150B. For example, the spacer structures 165 may comprise silicon nitride spacer elements possibly in combination with silicon dioxide etch stop materials (not shown). Furthermore, the transistors 150A, 150B comprise drain and source regions 153 that laterally confine the channel region 152. It should be appreciated that the drain and source regions 153 in the transistor 150A may have a different configuration compared to the drain and source regions 153 of the transistor 150B due to the different conductivity type. Similarly, the channel regions 152 may differ in their basic conductivity type. Furthermore, it is to be noted that the drain and source regions 153 may have any appropriate vertical and lateral dopant profile, for instance based on corresponding counter-doped areas and the like, in order to adjust the overall transistor characteristics. In the example shown, metal silicide regions 154 may be provided in the drain and source regions 153 in order to reduce the overall series resistance and the contact resistivity of the devices 150A, 150B.

Additionally, the semiconductor device 100 comprises at least a portion of an interlayer dielectric material 120 so as to laterally enclose the gate electrode structures 160A, 160B, wherein the dielectric material 120 may be comprised of a first dielectric material 121, such as a silicon nitride material, followed by a further dielectric material 122, such as silicon dioxide, as these two materials represent well-established dielectric materials for contact structures of sophisticated semiconductor devices.

The semiconductor device 100 as illustrated in FIG. 1 a may be formed on the basis of the following processes. After forming the active regions 103A, 103B by providing isolation structures and performing appropriate implantation processes based on appropriate masking regimes, the gate electrode structures 160A, 160B may be formed. For this purpose, materials for the layers 163 and 164 may be formed, for instance, by appropriate deposition techniques and/or surface treatments, followed by the deposition of the material 161, which may also be referred to as a placeholder material for the gate electrode structures 160A, 160B. Moreover, any additional materials, such as dielectric cap layers, such as silicon nitride materials, hard mask materials, for instance in the form of silicon oxynitride, amorphous carbon and the like, may additionally be deposited in order to enhance the patterning of the gate electrode structures 160A, 160B. Thereafter, sophisticated lithography and etch techniques may be applied in order to pattern the resulting material layer stack, thereby obtaining the gate electrode structures 160A, 160B comprising the material layers 163, 164 and 161. Consequently, during this patterning process, the basic geometry of the gate electrode structures 160A, 160B are defined. For example, a gate length, which is to be understood as the horizontal extension of the layers 163 and 164 in FIG. 1 a, may be adjusted to a value of 50 nm and less. Thereafter, the further processing is continued by forming the drain and source regions 153 in combination with the spacer structure 165, which may serve to confine the sensitive materials 163, 164 and provide a desired offset for implantation processes in order to define the lateral configuration of the drain and source regions 153. After any anneal processes for activating the dopants in the active regions 103A, 103B and for re-crystallizing implantation-induced damage, the metal silicide regions 154 may be formed by applying well-established silicidation techniques. Thereafter, the dielectric material 121 may be deposited, followed by the material 122, which may then be planarized in order to expose a surface of the polysilicon material 161 in the gate electrode structures 160A, 160B. Next, a wet chemical etch process is applied in order to remove the material 161 selectively with respect to the dielectric material 120, the spacer structure 165 and the conductive cap layer 164. For this purpose, TMAH (tetra methyl ammonium hydroxide) has been proven as a very efficient chemical agent which may be provided at elevated temperatures, thereby efficiently removing silicon material, while at the same time providing a high degree of selectively with respect to silicon dioxide, silicon nitride, titanium nitride and the like. Upon removing the placeholder material 161, the openings 162 are formed so as to receive the material layer 166A for adjusting the work function of the gate electrode structure 160A. For this purpose, the layer 166A is deposited by any appropriate deposition technique, such as sputter deposition, chemical vapor deposition (CVD) and the like, wherein the etch stop material 167 may be provided so as to enhance the further processing of the device 100. Consequently, a certain thickness of the material layer 166A may have to be provided within the openings 162, thereby resulting in a certain degree of overhangs 168 at the upper corners of the openings 162. Furthermore, the etch stop material 167 may have an influence on the finally obtained work function of the gate electrode structures 160A, 160B since the actual work function adjusting metal of the layer 166A may be offset from materials 164 and 163 by the layer 167. Consequently, a certain degree of threshold voltage shift may be induced in the transistors 150A and/or 150B during the further processing. After the deposition of the material layer 166A, an etch mask 104 is provided so as to cover the gate electrode structure 160A and expose the gate electrode structure 160B in which the work function adjusting species of the layer 166A is to be removed selectively with respect to the etch stop layer 167. For this purpose, typically, a resist material is applied and lithographically patterned into the mask 104. During this sophisticated patterning process, the resist material may not completely fill the opening 162 and may thus result in a pronounced varying surface topography, as indicated by 104A, which may result in a less reliable patterning sequence upon exposing and developing the resist material. This deterioration mechanism may also strongly depend on the degree of overhangs 168, since, for a short gate length, the effect of the overhangs 168 may increasingly influence the fill behavior of the resist material during the lithography process. Consequently, a reliable fill and thus protection of the material layer 166A during a subsequent wet chemical etch process 105 may be less reliable in sophisticated device geometries. During the etch process 105, the work function adjusting metal, which may comprise aluminum, titanium nitride and the like for P-channel transistors, may be removed selectively with respect to the etch stop layer 167, for instance in the form of tantalum nitride, which may be accomplished by using sulfuric acid in combination with hydrogen peroxide and the like.

FIG. 1 b schematically illustrates the semiconductor device 100 when exposed to a further reactive process ambient 106, in which the etch mask 104 (FIG. 1 a) is removed. For example, the process 106 may represent a plasma assisted process or a wet chemical etch process. Due to the sophisticated geometry of the openings 162, in particular in the gate electrode structure 160A which may still have the overhangs 168, it may become increasingly difficult to completely remove the resist material, which may thus result in resist residues 104R. Consequently, upon further processing the device 100, the residues 104R, possibly in combination with any process non-uniformities caused during the etch process 105 (FIG. 1 a), may result in a pronounced degree of variability of transistor characteristics of the transistor 150A and/or the transistor 150B. That is, process non-uniformities, in particular in the gate electrode structure 160A, may influence the further processing, i.e., the deposition of a further material layer including a work function metal for the transistor 150B and the deposition of an electrode metal, such as aluminum, thereby resulting in a significant yield loss in highly scaled semiconductor devices.

The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

Generally, the present disclosure relates to semiconductor devices and methods for forming the same in which gate electrode structures may be formed on the basis of a high-k dielectric material, wherein the work function for P-channel transistors and N-channel transistors may be adjusted on the basis of a replacement gate approach. Contrary to many conventional approaches, the placeholder material may be replaced individually for these transistors, thereby avoiding some of the problems associated with the patterning of one type of work function adjusting species. For example, in some illustrative aspects disclosed herein, a conductive etch stop layer that may be conventionally applied in combination with the actual work function species may no longer be necessary, thereby significantly enhancing the overall process uniformity and thus the characteristics of the finally obtained transistor elements. For example, the corresponding shift of the work function of one or both transistor types may be avoided or at least be significantly reduced.

One illustrative method disclosed herein comprises removing a placeholder material from a first gate electrode structure of a first transistor so as to form a first gate opening, while masking the placeholder material in a second gate electrode structure of a second transistor. The method further comprises forming a first material layer in the first gate opening, wherein the first material layer comprises a first work function metal. Additionally, the method comprises exposing a top surface of the placeholder material in the second gate electrode structure while preserving the first material layer at least at a bottom of the first gate opening. Moreover, the placeholder material of the second gate electrode structure is removed so as to form a second gate opening. Additionally, the method comprises forming a second material layer at least in the second gate opening, wherein the second material layer comprises a second work function metal that differs from the first work function metal.

A further illustrative method disclosed herein relates to forming gate electrode structures. The method comprises forming a first material layer in a first gate opening of a first gate electrode structure, wherein the first material layer comprises a first work function adjusting species. The method further comprises forming a second gate opening of a second gate electrode structure after forming the first material layer. Moreover, a second material layer is formed in at least the second gate opening, wherein the second material layer comprises a second work function adjusting species that differs from the first work function adjusting species. Additionally, the method comprises filling the first and second gate openings with an electrode material.

One illustrative semiconductor device disclosed herein comprises a first transistor that comprises a first gate electrode structure. The first gate electrode structure comprises a first gate insulation layer including a high-k dielectric material, a metal-containing cap material formed above the high-k dielectric material and a first work function adjusting material formed on the metal-containing cap material. The semiconductor device further comprises a second transistor comprising a second gate electrode structure. The second gate electrode structure comprises a second gate insulation layer including the high-k dielectric material, the metal-containing cap material and a second work function adjusting material formed on the metal-containing cap material.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

FIGS. 1 a-1 b schematically illustrate cross-sectional views of a sophisticated semiconductor device in which two different work function metals are applied in a late manufacturing stage according to a conventional replacement gate approach, thereby resulting in transistor non-uniformities;

FIGS. 2 a-2 j schematically illustrate cross-sectional views of a semiconductor device during various manufacturing stages when forming sophisticated gate electrode structures according to a replacement gate approach in which the placeholder materials of N-channel transistors and P-channel transistors are separately removed and wherein additional lithography processes for patterning a work function metal-containing material layer are avoided, according to illustrative embodiments; and

FIGS. 2 k-2 n schematically illustrate cross-sectional views of the semiconductor device according to still further illustrative embodiments in which a first work function metal may be removed from above a gate electrode structure which still comprises the placeholder material, thereby also improving the cross-sectional shape of the gate opening of the other transistor type.

While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.

The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below. 

1. A method, comprising: forming a first portion of an opening in a gate electrode structure of a transistor by removing a first portion of a placeholder electrode material of said gate electrode structure, said first portion of said opening having a width at a top area of said opening; increasing said width of said first portion of said opening at a top area thereof in the presence of a second portion of said placeholder electrode material; removing said second portion of said placeholder electrode material; forming a material layer in said opening having said increased width at the top area thereof, said material layer comprising a work function adjusting species; and filling said opening with a conductive electrode material.
 2. The method of claim 1, wherein increasing a width of said first portion of said opening comprises performing a plasma assisted etch process.
 3. The method of claim 2, wherein forming a first portion of said opening comprises performing said plasma assisted etch process so as to remove said first portion of said placeholder electrode material and to round corners of said opening.
 4. The method of claim 2, wherein removing said first portion of said placeholder electrode material comprises performing a first wet chemical etch process.
 5. The method of claim 1, wherein removing said second portion of said placeholder electrode material comprises performing a wet chemical etch process.
 6. The method of claim 5, wherein performing said wet chemical etch process comprises using a conductive cap layer formed above a gate dielectric material as an etch stop material.
 7. The method of claim 1, wherein filling a conductive electrode material into said opening comprises depositing said conductive electrode material so as to overfill said opening and removing excess material by performing at least one of an etch process and a polishing process.
 8. The method of claim 7, wherein removing excess material comprises removing material of said conductive electrode material and a portion of a dielectric material laterally delineating said opening so as to adjust a height of said gate electrode structure.
 9. The method of claim 1, further comprising forming a high-k dielectric material at least at the bottom of said opening prior to filling said conductive electrode material into said opening.
 10. The method of claim 1, further comprising forming a high-k dielectric material of said gate electrode structure prior to forming said opening.
 11. The method of claim 1, further comprising performing a cleaning process on said second portion of said placeholder electrode material after increasing said width.
 12. A method, comprising: removing a first portion of a placeholder electrode material of a gate electrode structure of a transistor, said placeholder electrode material being laterally enclosed by an insulating material; rounding corner areas of said insulating material in the presence of a second portion of said placeholder electrode material; removing said second portion by performing a wet chemical etch process so as to form an opening after rounding said corner areas; and forming a gate electrode in said opening.
 13. The method of claim 12, wherein rounding said corner areas comprises performing a plasma assisted etch process.
 14. The method of claim 12, wherein rounding said corner areas comprises performing a particle bombardment.
 15. The method of claim 14, wherein performing said particle bombardment comprises performing an ion sputtering process.
 16. The method of claim 12, further comprising performing a cleaning process on an exposed surface of said second portion prior to performing said wet chemical etch process.
 17. The method of claim 12, wherein removing said first portion of said placeholder electrode material comprises performing a first wet chemical etch process.
 18. The method of claim 12, wherein removing said first portion of said placeholder electrode material comprises performing a plasma based etch process.
 19. The method of claim 18, wherein performing said plasma based etch process comprises adapting at least one process parameter of said plasma based etch process so as to control a degree of material erosion at said corner areas.
 20. A semiconductor device, comprising: a gate electrode structure of a transistor formed above a semiconductor region, said gate electrode structure comprising a gate insulation layer including a high-k dielectric material and an electrode material formed on said gate insulation layer and having a tapered cross-sectional configuration, said gate electrode structure further comprising a work function adjusting material layer formed on sidewalls of said electrode material, a thickness of said work function adjusting material layer having a variation of less than 10 percent along said sidewalls.
 21. The semiconductor device of claim 20, wherein a length of said electrode material at said gate insulation layer is approximately 30 nm or less.
 22. The semiconductor device of claim 20, wherein said work function adjusting material layer comprises at least one of titanium and tantalum. 